* Cantinho Satkeys

Refresh History
  • FELISCUNHA: Bom dia pessoal   :34rbzg9:
    Hoje às 10:35
  • j.s.: :13arvoresnatalmagiagifs:
    21 de Dezembro de 2025, 19:01
  • j.s.: try65hytr a todos  :smiles_natal: :smiles_natal:
    21 de Dezembro de 2025, 19:01
  • FELISCUNHA: ghyt74  49E09B4F  e bom fim de semana  4tj97u<z
    20 de Dezembro de 2025, 11:20
  • JPratas: try65hytr Pessoal  2dgh8i k7y8j0 classic dgf64y
    19 de Dezembro de 2025, 05:26
  • cereal killa: ghyt74 e boa semana de chuva e frio  RGG45wj erfb57j
    15 de Dezembro de 2025, 11:26
  • FELISCUNHA: Votos de um santo domingo para todo o auditório  4tj97u<z
    14 de Dezembro de 2025, 09:28
  • j.s.: tenham um excelente fim de semana com muitas comprinhas  :13arvoresnatalmagiagifs: sdfgsdg
    13 de Dezembro de 2025, 14:58
  • j.s.: dgtgtr a todos  :smiles_natal:
    13 de Dezembro de 2025, 14:57
  • FELISCUNHA: dgtgtr   49E09B4F  e bom fim de semana   :34rbzg9:
    13 de Dezembro de 2025, 12:29
  • JPratas: try65hytr Pessoal  4tj97u<z 2dgh8i classic bve567o+
    12 de Dezembro de 2025, 05:34
  • FELISCUNHA: Votos de um santo domingo para todo o auditório  4tj97u<z
    07 de Dezembro de 2025, 11:23
  • j.s.: tenham um excelente domingo :smiles_natal:
    06 de Dezembro de 2025, 23:36
  • j.s.: try65hytr a todos :13arvoresnatalmagiagifs:
    06 de Dezembro de 2025, 23:36
  • FELISCUNHA: ghyt74 pessoal  :34rbzg9:
    05 de Dezembro de 2025, 11:58
  • JPratas: try65hytr Pessoal  4tj97u<z classic k7y8j0
    05 de Dezembro de 2025, 04:18
  • cereal killa: try65hytr pessoaal  :13arvoresnatalmagiagifs:  RGG45wj
    04 de Dezembro de 2025, 18:51
  • Bobo2009: Os nova
    01 de Dezembro de 2025, 21:02
  • FELISCUNHA: Votos de um santo domingo para todo o auditório   4tj97u<z
    30 de Novembro de 2025, 12:06
  • j.s.: tenham um excelente fim de semana  :smiles_natal:
    29 de Novembro de 2025, 14:19

Autor Tópico: Learn FPGA design with VHDL Driving an LCD Display  (Lida 58 vezes)

0 Membros e 1 Visitante estão a ver este tópico.

Online mitsumi

  • Sub-Administrador
  • ****
  • Mensagens: 129012
  • Karma: +0/-0
Learn FPGA design with VHDL Driving an LCD Display
« em: 26 de Julho de 2025, 10:56 »


Published 7/2025
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Language: English | Duration: 3h 31m | Size: 1.56 GB

Understand LCD display and build a VHDL controller from scratch with multiple Labs for practice


What you'll learn
Acquire skills to read and interpret a technical datasheet
Understand the internal structure of HD44780-compatible LCDs
Design a synthesizable LCD controller in VHDL
Structure your design using finite state machines (FSMs)
Manage multiple interacting FSMs
Best practices for modular, reusable, VHDL design
Hands-on practical labs (display text, display custom character, user-configurable countdown timer)
Requirements
Basic notions on digital electronics and VHDL are needed to get the most from this course
Description
As part of the "FPGA Design Using VHDL" hands-on series, this module focuses on driving character LCD displays - a fundamental interface for embedded systems and user interaction.In this course, you will:Learn how to read and interpret an LCD datasheetUnderstand the internal architecture of an LCD (DDRAM, CGRAM, CGROM, and instruction set)Design and implement a fully functional LCD controller in VHDLLearn how to connect and map LCD pins to your FPGA using proper I/O constraintsApply theoretical knowledge through practical design labsPractice LabsLab 1: Create a simple demo that displays "HELLO WORLD" using your VHDL LCD controllerLab 2: Generate and display a custom character (like a smiley face) on the LCDLab 3: Design a configurable countdown timer displayed in real-time on the LCD, with user input through buttons and switchesBy the end, you'll have the skills to read and understand a technical datasheet and integrate LCD displays into real-world VHDL projects with structured, reusable, and synthesizable code.Throughout the course, you'll also strengthen your understanding of Finite State Machines (FSMs) and learn to design multiple cooperating FSMs in a single FPGA system. You will practice interfacing, timing, and structuring logic for clarity and reliability - skills essential for professional digital design.
Who this course is for
Beginner Digital Electronics students and engineers or anyone interested in learning FPGA design
Homepage:
Código: [Seleccione]
https://www.udemy.com/course/learn-fpga-design-with-vhdl-driving-an-lcd-display/
Screenshots


Download link

rapidgator.net:
Citar
https://rapidgator.net/file/0789ddd479ef91d23cc0f2cf774f3a5e/eteub.Learn.FPGA.design.with.VHDL..Driving.an.LCD.Display.part1.rar.html
https://rapidgator.net/file/ed72f803e185b9fffe7a031d16254448/eteub.Learn.FPGA.design.with.VHDL..Driving.an.LCD.Display.part2.rar.html

nitroflare.com:
Citar
https://nitroflare.com/view/EA8930F127E52B8/eteub.Learn.FPGA.design.with.VHDL..Driving.an.LCD.Display.part1.rar
https://nitroflare.com/view/89B797F2A3EDE68/eteub.Learn.FPGA.design.with.VHDL..Driving.an.LCD.Display.part2.rar