* Cantinho Satkeys

Refresh History
  • FELISCUNHA: ghyt74  pessoal  4tj97u<z
    21 de Abril de 2025, 10:38
  • cereal killa:
    19 de Abril de 2025, 21:17
  • j.s.: tenham uma Santa e Feliz Páscoa  49E09B4F 49E09B4F 49E09B4F
    19 de Abril de 2025, 18:19
  • j.s.:
    19 de Abril de 2025, 18:19
  • j.s.: dgtgtr a todos  4tj97u<z 4tj97u<z
    19 de Abril de 2025, 18:15
  • FELISCUNHA: Uma santa sexta feira para todo o auditório  4tj97u<z
    18 de Abril de 2025, 11:12
  • JPratas: try65hytr Pessoal  4tj97u<z classic k7y8j0
    18 de Abril de 2025, 03:28
  • cereal killa: try65hytr malta  classic 2dgh8i
    14 de Abril de 2025, 23:14
  • FELISCUNHA: Votos de um santo domingo para todo o auditório  101041
    13 de Abril de 2025, 11:45
  • j.s.: e um bom domingo de Ramos  43e5r6 43e5r6
    11 de Abril de 2025, 21:02
  • j.s.: tenham um excelente fim de semana  49E09B4F
    11 de Abril de 2025, 21:01
  • j.s.: try65hytr a todos  4tj97u<z
    11 de Abril de 2025, 21:00
  • JPratas: try65hytr  y5r6t Pessoal  classic k7y8j0
    11 de Abril de 2025, 04:15
  • JPratas: dgtgtr A Todos  4tj97u<z classic k7y8j0
    10 de Abril de 2025, 18:29
  • FELISCUNHA: ghyt74  pessoal   49E09B4F
    09 de Abril de 2025, 11:59
  • cereal killa: try65hytr pessoal  2dgh8i
    08 de Abril de 2025, 23:21
  • FELISCUNHA: Votos de um santo domingo para todo o auditório  43e5r6
    06 de Abril de 2025, 11:13
  • cccdh: Ola para todos!
    04 de Abril de 2025, 23:41
  • j.s.: tenham um excelente fim de semana  49E09B4F
    04 de Abril de 2025, 21:10
  • j.s.: try65hytr a todos  4tj97u<z
    04 de Abril de 2025, 21:10

Autor Tópico: Randomization and IPC in SystemVerilog  (Lida 82 vezes)

0 Membros e 1 Visitante estão a ver este tópico.

Online mitsumi

  • Moderador Global
  • ***
  • Mensagens: 119261
  • Karma: +0/-0
Randomization and IPC in SystemVerilog
« em: 02 de Julho de 2021, 14:57 »

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English | Duration: 47 lectures (12h 42m) | Size: 3 GB
Simple course to learn advanced verification technique of Randomization and IPC in SystemVerilog.

What you'll learn:
Difference between directed and random testing
What is randomization and why verifiation engineer should know it
How to do ramdomization in SystemVerilog
How to do constrained randomization
Various options available during randomization
How control thread execution happens in Verilog
Event communication in SystemVerilog
Semaphore in SystemVerilog
Mailboxes in SystemVerilog
How to write Testbench using IPC

Requirements
It is expected that knowledge of fundamentals of verification and basic constructs of SystemVerilog are known
Familiarity with Object Oriented Programming is an added advantage
Verilog programming and fundamentals of FPGA programming are supposed to be already known

Description
VLSI industry requires more verification engineers and less design engineers. Roughly this ratio is around 70 to 30 percent respectively. Because todays designs are not only very complex but also challenging to verify due to technological advancements at all the levels of design. There are many techniques that are required to be known to today's verification engineers. How to design powerful and flexible test bench is always a challenge for verification engineers. SystemVerilog provides various constructs which can ease the job of verification engineer. However one should have basic knowledge about those constructs.

This course is introduced for learners who wants to learn advanced verification techniques of randomization and inter-process communication (IPC) in SystemVerilog. It is assumed that learner is aware of the basic constructs of SystemVerilog and object oriented programming. In this course, students will learn when to do randomization, how to do constraint randomization, what are various inter-process communication techniques etc. Various IPC techniques like events, semaphores and mailboxes will be introduced. Course is being taught with various examples and learner can monitor self-progress by attempting quiz in each section. Students can try to simulate all the examples discussed in the course in EDA Playground and verify the theoretical concepts. After learning this course, students will be able to apply randomization and IPC techniques while designing test bench.

Who this course is for
This course is for students and engineers who wants to learn basics of randomization and IPC in short time.
Verification engineers who wants to refresh concepts of randomization and IPC.


Download link:
Só visivel para registados e com resposta ao tópico.

Only visible to registered and with a reply to the topic.

Links are Interchangeable - No Password - Single Extraction