* Cantinho Satkeys

Refresh History
  • Gerard: j'espère que tous sont en train d'être bem
    12 de Setembro de 2025, 13:28
  • Gerard: Boas tardes
    12 de Setembro de 2025, 13:26
  • FELISCUNHA: ghyt74   49E09B4F  e bom fim de semana   4tj97u<z
    12 de Setembro de 2025, 11:51
  • JPratas: try65hytr Pessoal  4tj97u<z classic k7y8j0
    12 de Setembro de 2025, 03:29
  • yaro-82: 1994
    07 de Setembro de 2025, 16:49
  • FELISCUNHA: Votos de um santo domingo para todo o auditório  43e5r6
    07 de Setembro de 2025, 10:52
  • j.s.: tenham um excelente fim de semana  49E09B4F
    06 de Setembro de 2025, 17:07
  • j.s.: dgtgtr a todos  4tj97u<z
    06 de Setembro de 2025, 17:07
  • FELISCUNHA: Boa tarde pessoal  49E09B4F bom fim de semana  htg6454y
    05 de Setembro de 2025, 14:53
  • JPratas: try65hytr A Todos  4tj97u<z classic k7y8j0
    05 de Setembro de 2025, 03:10
  • cereal killa: dgtgtr pessoal  4tj97u<z
    03 de Setembro de 2025, 15:26
  • FELISCUNHA: ghyt74  pessoal   49E09B4F
    01 de Setembro de 2025, 11:36
  • j.s.: de regresso a casa  535reqef34
    31 de Agosto de 2025, 20:21
  • j.s.: try65hytr a todos  4tj97u<z
    31 de Agosto de 2025, 20:21
  • FELISCUNHA: ghyt74   49E09B4e bom fim de semana  4tj97u<z
    30 de Agosto de 2025, 11:48
  • henrike: try65hytr     k7y8j0
    29 de Agosto de 2025, 21:52
  • JPratas: try65hytr Pessoal 4tj97u<z 2dgh8i classic k7y8j0
    29 de Agosto de 2025, 03:57
  • cereal killa: dgtgtr pessoal  2dgh8i
    27 de Agosto de 2025, 12:28
  • FELISCUNHA: Votos de um santo domingo para todo o auditório  4tj97u<z
    24 de Agosto de 2025, 11:26
  • janstu10: reed
    24 de Agosto de 2025, 10:52

Autor Tópico: Embedded System Design with Zynq Devices for Newbie  (Lida 139 vezes)

0 Membros e 1 Visitante estão a ver este tópico.

Offline mitsumi

  • Sub-Administrador
  • ****
  • Mensagens: 124987
  • Karma: +0/-0
Embedded System Design with Zynq Devices for Newbie
« em: 13 de Maio de 2021, 11:11 »

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + srt | Duration: 63 lectures (7h 46m) | Size: 3 GB
All about Xil Drivers, Interrupts, Custom AXI Peripherals , Debugging and Profiling

What you'll learn:
Embedded System Design flow using Zynq AP SoC
Software and Hardware Debugging
Fundamentals strategies to use Xilinx Drivers
Software Profiling
Interrupts
Development of C applications for Zynq Devices

Requirements
Understanding of Digital Electronics
Fundamentals of Computer Architecture

Description
Xilinx Zynq SoC's are capable of providing maximum performance per watt along with maximum reconfiguration flexibility. Zynq family features Dual-Core ARM Cortex A9 processors tightly coupled with the 7-series FPGA to enable faster communication interfaces development with ARM Design flow and hardware acceleration. Zynq devices are available in two categories viz. Zynq-7000s family FPGA for the cost-effective application such as IoT related applications while Zynq 7000 family FPGA are best for high-performance applications such as Embedded Vision etc. The Zynq 7000s comes with Single core ARM while Zynq 7000 comes with Dual-Core ARM.

This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Zynq based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Zynq to felicitate performance measurement.

This course will create the foundation necessary to quickly start building applications on Zynq FPGA devices without prior experience in this domain. The entire course is a Lab-based course with a major focussed on building skills necessary to handle simple peripherals such as GPIO, Intermediate Peripherals such as UART PS, AXI BRAM, and complex Peripherals such as AXI Interrupt Controller, AXI Timers, GIC etc.

Who this course is for
Anyone wish to build expertise in Xilinx Zynq APSOC and Vivado SDK Environment
Embedded System Design with FPGA Processors


Download link:
Só visivel para registados e com resposta ao tópico.

Only visible to registered and with a reply to the topic.

Links are Interchangeable - No Password - Single Extraction