* Cantinho Satkeys

Refresh History
  • Gerard: j'espère que tous sont en train d'être bem
    12 de Setembro de 2025, 13:28
  • Gerard: Boas tardes
    12 de Setembro de 2025, 13:26
  • FELISCUNHA: ghyt74   49E09B4F  e bom fim de semana   4tj97u<z
    12 de Setembro de 2025, 11:51
  • JPratas: try65hytr Pessoal  4tj97u<z classic k7y8j0
    12 de Setembro de 2025, 03:29
  • yaro-82: 1994
    07 de Setembro de 2025, 16:49
  • FELISCUNHA: Votos de um santo domingo para todo o auditório  43e5r6
    07 de Setembro de 2025, 10:52
  • j.s.: tenham um excelente fim de semana  49E09B4F
    06 de Setembro de 2025, 17:07
  • j.s.: dgtgtr a todos  4tj97u<z
    06 de Setembro de 2025, 17:07
  • FELISCUNHA: Boa tarde pessoal  49E09B4F bom fim de semana  htg6454y
    05 de Setembro de 2025, 14:53
  • JPratas: try65hytr A Todos  4tj97u<z classic k7y8j0
    05 de Setembro de 2025, 03:10
  • cereal killa: dgtgtr pessoal  4tj97u<z
    03 de Setembro de 2025, 15:26
  • FELISCUNHA: ghyt74  pessoal   49E09B4F
    01 de Setembro de 2025, 11:36
  • j.s.: de regresso a casa  535reqef34
    31 de Agosto de 2025, 20:21
  • j.s.: try65hytr a todos  4tj97u<z
    31 de Agosto de 2025, 20:21
  • FELISCUNHA: ghyt74   49E09B4e bom fim de semana  4tj97u<z
    30 de Agosto de 2025, 11:48
  • henrike: try65hytr     k7y8j0
    29 de Agosto de 2025, 21:52
  • JPratas: try65hytr Pessoal 4tj97u<z 2dgh8i classic k7y8j0
    29 de Agosto de 2025, 03:57
  • cereal killa: dgtgtr pessoal  2dgh8i
    27 de Agosto de 2025, 12:28
  • FELISCUNHA: Votos de um santo domingo para todo o auditório  4tj97u<z
    24 de Agosto de 2025, 11:26
  • janstu10: reed
    24 de Agosto de 2025, 10:52

Autor Tópico: FPGA Embedded Design, Part 2 - Basic FPGA Training  (Lida 128 vezes)

0 Membros e 1 Visitante estão a ver este tópico.

Offline mitsumi

  • Sub-Administrador
  • ****
  • Mensagens: 124987
  • Karma: +0/-0
FPGA Embedded Design, Part 2 - Basic FPGA Training
« em: 07 de Abril de 2021, 11:20 »
MP4 | Video: h264, 1280x720 | Audio: AAC, 44100 Hz
Language: English | Size: 1.36 GB | Duration: 2h 44m

What you'll learn
Build an FPGA embedded solution from the ground up using Altera/Intel FPGAs and software.
Apply your Verilog knowledge to real applications with FPGAs.
Requirements
Basic knowledge of Hardware Description languages like Verilog or VHDL is expected.
You are not required to make any purchases, but an Altera/Intel DE0-CV board will come in handy if you want to follow along with the examples shown throughout the course.
Description
It's time to get your hands on an actual FPGA!

In this second part of the FPGA Embedded Design series, we'll get our hands on an actual FPGA to bring our designs to life.

We'll use an FPGA development board from Terasic. We'll program a Cyclone V FPGA from Altera/Intel, using their development suite Quartus Prime.

This course consists of two main parts:

Foundations of FPGAs, where we'll cover the essentials of FPGAs, how they work, what they can and cannot do.

Hands-On Training, where we'll design some simple hardware and download it into an FPGA development board. No purchases are required for this second part, but it sure helps to have your own board to follow along, and keep on tinkering in the future with this new superpower.

What are you waiting for? Let's have some fun!!!

Who this course is for:
Anyone who wants to learn FPGA design.
Developers curious about FPGA Design.
Embedded Engineers who want to learn about FPGAs.
This course is not for experienced embedded engineers specialized in FPGAs.

Screenshots


Download link:
Só visivel para registados e com resposta ao tópico.

Only visible to registered and with a reply to the topic.

Links are Interchangeable - No Password - Single Extraction