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Autor Tópico: VIVADO - regular FIFO vs AXI FIFO  (Lida 95 vezes)

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VIVADO - regular FIFO vs AXI FIFO
« em: 12 de Maio de 2021, 13:37 »
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + .srt | Duration: 8 lectures (2 hour, 5 mins) | Size: 1.52 GB
Learn what FIFO is and how to use FIFO IP Cores of Vivado Xilinx FPGA tool

What you'll learn

Fundamentals of a FIFO
Differences between regular FIFO to AXI FIFO
Main uses for FIFOs
How to read and write a regular FIFO VS AXI FIFO
How to simulate the FIFOs
About FIFOs with 2 different clocks for read and write and when should we use it

Requirements

Basic knowledge of VIVADO is required

Description

In this course you will what FIFO is and how to use it with VIVADO Xilinx FPGA tool.

This course was created for students who wants to know more about FIFOs.

Beside Xilinx VIVADO tool, this course will help you getting the fundamentals about FIFOs.

I will show you how to implement VIVADO built in FIFO IP cores and how to use them.

I will introduce you to 2 of the most commons FIFO, Regular FIFO and AXI FIFO.

We will go through their settings and I will explain you about both of them.

You will learn how to read and write to the FIFOs and how to simulate it.

I will explain you and show you what is the difference between FIFO with one clock for read/write to FIFO with 2 different clocks, one for read and one for write...

Far more I will explain why and where do we use a FIFO with 2 different clocks

In the end of this course you will be able to use FIFOs without any problem in any tool you want.

This course is for anyone who wants to learn more about FIFOs and is mostly great for beginners who doesn't have any background with FIFOs.

Who this course is for:

Anyone who wants to get familiar with FIFOs uses and implementations
Anyone who wants to know how transfer data between components with different clocks from each other
Anyone who wants to know more about VIVADO FIFOs options

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