ASAP 7nm PDK version 1p7
ASAP 7nm PDK version 1p7 | 4.5 Gb
The Lawrence Clark, an Emeritus Professor in the School of Electrical, is pleased to announce the availability of ASAP 7nm PDK version 1p7. This PDK contains SPICE-compatible FinFET device models (BSIM-CMG), Technology files for Cadence Virtuoso, Design Rule Checker (DRC), Layout vs Schematic Checker (LVS) and Extraction Deck for the 7nm technology node.
Academic research in VLSI design and CAD, especially for advanced technology nodes has been severely limited by the lack of quality process design kit (PDK). Most advanced technology circuit and CAD research employ either SPICE-only predictive technology models or scale 45nm OpenPDK libraries to sub-10 or 7nm node dimensions. These methods omit important effects such as layout-dependent middle-of-line (MOL) parasitics, BEOL parasitics, multiple patterning effects, etc. As a result, even though academics pursue relevant CAD and VLSI research topics, the results and observations are not always reliable. For CAD research, utilizing scaled GDS/LEF layout files from 45nm technology node to sub-14nm dimensions can lead to erroneous conclusions and the researchers might not be even targeting the relevant problems. To bridge this gap, the ASAP7 PDK targeting the 7nm process node was developed in 2016 as a joint collaboration between ARM and Arizona State University for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any specific foundry.
The PDK contains SPICE-compatible FinFET device models (BSIM-CMG), Technology files for Cadence Virtuoso, Design Rule Checker (DRC), Layout vs Schematic Checker (LVS) and Extraction Deck for the 7nm technology node.
Lawrence Clark is an Emeritus Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He has approximately 15 years of industy experience at Intel and VLSI Technology Inc. He contributed to a number of miroprocessor and chipset designs and was most recently a principal engineer and circuit design manager for the Xscale microprocessors. He also worked on compact modeling, reliability modeling and CMOS imagers.
His areas of expertise include low power high performance VLSI radiation hardening and harsh environment VLSI CAD and device behavior for VLSI
Product: ASAP 7nm PDK
Version: 1p7 *
Supported Architectures: x64
Website Home Page :
http://asap.asu.edu/Language: english
System Requirements: Linux *
Size: 4.5 Gb
asap7PDK_r1p7 : ASAP7 PDK (version 1p7)
asap7sc7p5t_27 : ASAP7 7.5-Track Cell Library (version 27)
This PDK version has been tested with Calibre 'aoi_cal_2017.4_19.14' and was found to be functional. This PDK version was found to be incompatible with the xACT extraction engine in Calibre 'aoi_cal_2018.2_52.40'. It is likely that other Calibre versions that succeed 'aoi_cal_2017.4_19.14' may be incompatible as well.
The Calibre tool environment is available through the Virtuoso toolbar. The DRC, LVS, and xACT runsets have been supplied with the PDK.
Other CAD Tool Support
- Cadence Virtuoso-Schematic and layout
- SPICE models (BSIM-CMG) from netlister
- Mentor Calibre DRC, LVS, PEX (xACT3D)
DOWNLOAD LINKS :
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