Mentor Graphics QuestaSim 10.7c

[mitsumi]

Mentor Graphics QuestaSim 10.7c | 5.0 Gb

Mentor, a Siemens business, has unveiled QuestaSim 10.7c  comprehensive platform for verification complex designs. Questa is built on a core simulation and debug engine providing the industry's most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF.

        New Features Contained in this Release:
- Improved VHDL performance - memories, clocks, composites
- Gate Level add_seq_delay and other optimizations
- Improved access write performance
- Early access support of IEEE 1735 version 2 cryptography
- Deprecated old -novopt flow, option to be removed in next release

General Enhancements in 10.7c
QSIM-879 - Added support for matching bit-blasted scalar port in rtl with normal non-escaped port names in SDF under switch "-sdfallowvlogescapeport".
User Interface Enhancements in 10.7c
QSIM-35477 - The SourceDir variable has improved the remapping behavior for finding source files. Instead of having to define each source directory location, defining a single root source directory should be sufficient to find any source file within the directory sub-tree, as long as the sub-tree path is the same as the original.
SystemVerilog Enhancements in 10.7c
[nodvtid] - Verilog design units' library signatures have changed from previous versions of 10.7. This requires a refresh when using previous 10.7 libraries in 10.7c.

User Interface Defects Repaired in 10.7c
QSIM-21724 - The logging of nets or registers of types containing SV unions has several issues which would lead to crashes or the display of incorrect data. These issues have been resolved.
SystemVerilog Defects Repaired in 10.7c
QSIM-50272 - The vencrypt feature "-auto3protect" could not properly handle macro call syntax in the port list of a module.
QSIM-17634 - (results) Optimized cell path delays could be incorrectly shortened when used with negative timing checks.
QSIM-8147 - (results) Restart with designs having negative timing check limits could effect simulation timing checks and functional evaluation behavior.
VHDL Defects Repaired in 10.7c
QSIM-5497 - For some specific cases of type conversions used in the unbound components, vsim used to crash. This has been fixed.
QSIM-10698 - The verilog reserved word "global" was not supported in VHDL packages with -mixedsvvh switch. This has been supported now.
VISU-4153 - (results) When logging VHDL to a qwave file, contents of standard IEEE packages, like stdlogic and numeric_std are not included. Now packaged like fixed_pkg and float_generic_pkg are also excluded. Standard packages beginning with "float" or "fixed" are filtered out of logging.
QSIM-43580 - A port association that is an aggregate with an OTHERS choice, for a constrained port that is an array-of-array, and where those constraints are globally static, could result in either a compiler internal error or a run-time simulator error about mismatched array lengths.
QSIM-26474 - In certain specific cases usage of slice expressions inside loop statements used to result in a crash. This has been fixed.
QSIM-32597 - In certain specific cases usage of nested if statements resulted in a crash due to certain optimizations. This has been fixed.
QSIM-50516 - In some case vopt generate an internal error or bad code for a configuration. This would occur if a generic or port of a component being configuration was used anywhere other than the port/generic map.
QSIM-50659 - (results) In certain cases where an actual is connected to multiple formals of a procedure, the simulation output was incorrect. This has been fixed.
QSIM-3588 - For some specific cases of for generates, vsim use to crash. This has been fixed.
Verification Management Defects Repaired in 10.7c
VM-8783 - Fixed bug where "-inputsfile" option to "triage passfail" command wasn't being recognized.   
   

QuestaSim      is part of the Questa Advanced Functional Verification Platform and is                                                                                                                                                                                                         the latest tool in Mentor Graphics tool suite for Functional Verification. The tool provides simulation support for latest standards of SystemC, SystemVerilog, Verilog 2001 standard and VHDL. This tool is an advancement over Modelsim in its support for advanced Verification features like coverage databases, coverage driven verification, working with assertions, SystemVerilog constrained-random functionality.

Mentor Graphics     is a technology leader in electronic design automation (EDA), providing software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. The company offers innovative products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design. Mentor Graphics has the broadest industry portfolio of best-in-class products and is the only EDA company with an embedded software solution.

Product: Mentor Graphics QuestaSim
Version: 10.7c
Supported Architectures: 32bit / 64bit
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Language: english
System Requirements: PC / Linux *
Supported Operating Systems: *
Size: 5.0 Gb

        Base Product Specifications in 10.7c

Supported Platforms
- Linux RHEL 6 x86/x86-64
- Linux RHEL 7 x86/x86-64
- Linux SLES 11 x86/x86-64
- Linux SLES 12 x86/x86-64
- Windows 7 x86/x64
- Windows 8.1 x86/x64
- Windows 10 x86/x64

Supported GCC Compilers (for SystemC)
- gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64
- gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64
- gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
- gcc-4.2.1-mingw32vc12

OVL (shipped with product)
v2.8.1

VHDL OSVVM (shipped with product)
v2014.07   

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