Cadence SPB Allegro and OrCAD 17.20.000-2016 HF055
Cadence SPB Allegro and OrCAD 17.20.000-2016 HF055 | 3.8 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled a new of improvements to the Cadence SPB Allegro and OrCAD 17.20 families of products aimed at boosting performance and productivity through improvements features and big fixed issues.
ADW PART_BROWSER Symbol Graphics preview is not available in the Designer Server
- ADW PART_BROWSER Component Browser is not displaying the symbol & footprint preview
- ALLEGRO_EDITOR 3D_CANVAS Floating parts on bending a board in 3D Canvas with HotFix 053
- ALLEGRO_EDITOR ARTWORK Incorrect Gerber import in Allegro PCB Editor
- ALLEGRO_EDITOR DATABASE axlDeleteByLayer deletes fixed shapes
- ALLEGRO_EDITOR DATABASE Release 17.2-2016: Board file saved in HotFix 049 cannot be opened in HotFix 014
- ALLEGRO_EDITOR DFM Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit
- ALLEGRO_EDITOR DRAFTING Angular dimension not owned by the same parent symbol in the layout are not deleted on moving object
- ALLEGRO_EDITOR INTERACTIV Place replicate module bounding box does not move with circuit after module is updated
- ALLEGRO_EDITOR MANUFACT Stackup chart and table shift slightly from original location on re-generation in Allegro PCB Editor release 17.2-2016
- ALLEGRO_EDITOR MCAD_COLLAB Selected objects deleted from the design on clicking Cancel in IDX Flow Manager Import
- ALLEGRO_EDITOR MCAD_COLLAB IDX outputs two sets of masks
- ALLEGRO_EDITOR NC Artwork file error for via size
- ALLEGRO_EDITOR PLACEMENT Setting PSMPATH: axlSetVariableFile() does not update Place Manual but User Preference Editor does
- ALLEGRO_EDITOR PLACEMENT Get import errors and cannot place some parts if user-defined option is turned on for netlist import
- ALLEGRO_EDITOR PLACEMENT Cannot place part because attribute definitions are incompatible for the 'DESCRIPTION' attribute (SPMHDB-154)
- ALLEGRO_EDITOR SCHEM_FTB Import Logic takes a long time when checks are turned on
- ALLEGRO_EDITOR SHAPE Shape Degassing crashes if 'Inside Shape' is selected
- ALLEGRO_EDITOR SHAPE Symbol Editor stops responding on editing shape with a .dra file
- ALLEGRO_EDITOR SKILL axlPadSuppressSet does not work when 'none' switch is used
- ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'off 'none ) returns a warning message and does not work per the documentation
- ALLEGRO_EDITOR SKILL Syntax error related to allegro.ini shown if allegro.ilinit loads INI on startup
- ALLEGRO_EDITOR SRM RF elements are shown in Symbol Revision Manager
- ALLEGRO_EDITOR TESTPREP Testprep re-sequence causes PCB Editor to crash if 'Labels with Net Name' is selected
- ALLEGRO_PROD_TOOLB CORE Productivity Toolbox bar code generator is creating corrupted shapes in the database
- ALTM_TRANSLATOR CAPTURE Third-party import fails
- ALTM_TRANSLATOR CAPTURE Third-party CAD translation stopped with error message
- ALTM_TRANSLATOR DE_HDL Cannot translate third-party to Allegro Design Entry HDL
- ALTM_TRANSLATOR PCB_EDITOR Third-party translation converts to board with unconnected nets
- ALTM_TRANSLATOR PCB_EDITOR Third-party board file: copper not imported
- ALTM_TRANSLATOR PCB_EDITOR Third-party to Allegro PCB Editor import issues with routes, constraints, size, and accuracy
- ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not show any results on PCB Editor canvas
- APD DIE_EDITOR Mirror Geometry is Mirroring the symbol from TOP to BOTTOM Layer in SIP file
- APD DIE_EDITOR Applying mirror geometry results in mirroring: moved from TOP to BOTTOM layer
- APD OTHER Duplicate layer text shown on the vias
- CIS CONFIGURATION Auto Symbol Refresh Checking not working for shared folders
- CONCEPT_HDL CORE Hierarchy Viewer expands/collapses randomly after clicking the '+' or '-' symbols
- CONCEPT_HDL CORE Copyproject does not properly copy the variant files
- CONCEPT_HDL CORE DE-HDL: very slow rendering on some systems
- CONCEPT_HDL CORE Getting 'Variant out of sync' warning when creating BOM for a design with no variants
- CONCEPT_HDL CORE Lower-level signals are appended with _1, _2, and so on
- CONCEPT_HDL CORE The physical net names still do not sync with the assigned signal name
- CONCEPT_HDL GLOBALCHANGE Global Property Delete does not operate on the entire design unless the top-level page 1 is open
- SIG_EXPLORER OTHER Signal explorer invocation with OrCAD PCB Expert Suite license
- SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
- SYSTEM_CAPTURE CANVAS_EDIT Symbols take a long time to move, and results in DRCs and broken connections
- SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks
- SYSTEM_CAPTURE MISCELLANEOUS cds.lib file is picked up from wrong location
- SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture prevents a project from opening by putting a single quote at the end of a line in CPM file
- SYSTEM_CAPTURE OPEN_CLOSE_PR The 'enable pspice' entry in CPM file is occasionally corrupted
About SPB Allegro and OrCAD 17.20-2016. Cadence Design Systems announced new capabilities for OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
This OrCAD portfolio includes new advanced technology enabled for integrated rigid-flex planning, design and real-time visualization, as well as built-in translators that enable direct design imports from select EDA vendors. PSpice Designer now supports system-level simulation using C/C++/SystemC and VerilogA, via the new PSpice compact model interface. This enables hardware/software virtual prototyping so that electrical engineers can design and simulate intelligent IoT devices. OrCAD is the only fully scalable PCB design solution available in the market that seamlessly transitions from mainstream to enterprise PCB solution with the Allegro environment.
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD portfolio uses a new multi-stack-up database capability and extensive in-design inter-layer checks, which helps users avoid errors introduced through manual checking. The OrCAD portfolio also features enhancements targeted towards improving PCB editors' productivity and ease-of-use in padstack editing, constraint management, shape editing and in-design DRCs. To address efficiency needs, the portfolio includes an advanced design differencing engine that enables design review with global teams using state of art visuals. Finally, to give designers more control over their design component annotation process, advanced annotation and auto-referencing capabilities are now available.
Allegro 17.2 release introduces many new capabilities for Flex and Rigid-Flex designs.
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence SPB Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF055
Supported Architectures: x64
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