Aldec Active-HDL 13.0.375.8320
Aldec Active-HDL 13.0.375.8320 | 577.5 mb
Aldec, Inc.
, a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, advances VHDL's verification capabilities with Active-HDL, version 13.0. This latest release introduces support for VHDL-2019 protected types with generics, composites of protected types, pointers to objects of protected types and composition with protected types.
Protected types were introduced in VHDL-2000 to allow the creation of class-like objects (similar to classes in C), which then later became required for shared variables in VHDL-2002. In VHDL-2019, the capabilities of protected types have been significantly improved to address new use models essential for the creation of complex testbenches that require advanced data structures.
Protected types are a powerful mechanism for creating functional coverage, random test generation, messaging, unified error reporting and verification data structures such as memory models, FIFOs and scoreboards.
Eeers can also use protected types on an entity interface for sharing a single memory among multiple AXI4 memory-mapped external peripherals, ideal for verifying SoC FPGAs used for multi-sensor data aggregation.
is an integrated environment designed for development of VHDL, Verilog/SystemVerilog, EDIF, and SystemC designs. It comprises of several design entry tools, HDL/SystemC compiler, single simulation kernel, several standard and advanced debugging tools, graphical and textual simulation output viewers, and many auxiliary utilities designed for easy management of designs, resource files, and libraries as well as built-in interfaces that allow running simulation, synthesis, or implementation locally or on remote computers, controlling revision of source files, or communicating with third-party tools that provide simulation models.
In addition, Active-HDL provides a set of powerful wizards which facilitate creation of new workspaces, designs or design resources including VHDL, Verilog, SystemC source files, block or state diagrams, testbenches, etc.
Most operations that you perform from the graphical user interface can be also invoked through the commands of the Active-HDL macro language. By writing your own macros, you can significantly improve testing and automate design processing. Active-HDL also provides scripting ees for Perl and Tcl/Tk. By creating user-defined scripts, you can enhance Active-HDL design environment by adding additional windows, extending the macro language, and providing interfaces to external tools and software products.
The Active-HDL suite also includes VSimSA, a standalone VHDL/Verilog/SystemVerilog/EDIF/SystemC simulation environment designed for batch processing. Functionally, VSimSA is entirely independent of Active-HDL. What distinguishes VSimSA from Active-HDL is the lack of a graphical user interface (GUI). VSimSA commands and programs are issued and controlled exclusively from a command-line, which is especially useful in an automated design testing.
Active-HDL 13 provides many new features and enhancements that simplify team-based design, increase design productivity and the speed of behavioral, RTL, and timing simulation of VHDL, Verilog, SystemC, SystemVerilog and EDIF projects.
is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.
Aldec Active-HDL
13.0.375.8320
x64 english
Windows *
577.5 mb
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