Learn VHDL from the beginning for FPGA and CPLD development

[mitsumi]

MP4 | Video: h264, 1280x720 | Audio: AAC, 44100 Hz
Language: English | Size: 4.35 GB | Duration: 10h 16m

In this course you will learn how to write VHDL code for FPGAs/CPLDs No prior VHDL or FPGA knowledge is needed. This course is designed from the basic elements you need to know about VHDL code. The course built in such way that you will learn first about the FPGAs and CPLDs structure so you will have a basic knowledge what are you going to do when you are writing a VHDL code.
We will go through all the basic elements of the VHDL code Starting from the VHDL code structure of a basic code to the structure of more advanced coding. After learning about the structure you will learn about the data types, VHDL basic design units, VHDL advanced design units, VHDL statements format.
You will learn about the Clock and Resets of the FPGA and how to use them FPGAs/CPLDs are actual components that receiving real signals from the outside world. Some of them will be synchronized signals that has a clock. You will learn how to use the clocks and the resets to sample new data and create data/communication with the outside world.
The course contains over 50 lectures that will teach you the syntax of the VHDL code
In the end of the course we will complete together 6 Exercises You will learn how to code the VHDL by practice. Starting from the most basic VHDL code with Increasing task difficulty enhances I will show you in these videos how to write the code in the right way.
In the end of the course I will upload the last exercise code to a real FPGA! (with my Xilinx development board) I will also show you in real-time how I can debug the code with a real time debugger which is the Integrated logic analyzer of Xilinx.
This Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market.

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