Keysight ADS 2020 Update 2
Keysight ADS 2020 Update 2 | 2.1 Gb
The PathWave development team is pleased to announce the availability of Advanced Design System (ADS) 2020 Update 2. This version provides several key enhancements for high-speed digital designers. Including enhancements to Memory Designer, DDR5 Compliance support, and a new end-to-end electrical-optical link with VPI Photonics.
Keysight has announced the release of its updated PathWave * Design 2020 software suite. The new suite includes updates to the electronic design automation software to accelerate design workflows for radio frequency (RF) and microwave, 5G, and automotive design engineers. The new releases of flagship products included in the software suite are: PathWave Advanced Design System (ADS) 2020, PathWave RFIC Design (GoldenGate) 2020, PathWave System Design (SystemVue) 2020, and PathWave RF Synthesis (Genesys) 2020.
The PathWave * Design 2020 software suite accelerates product development by reducing the time engineers spend in the design and simulation phase. Its libraries and customized simulators reduce setup time and automation improvements reduce manual work. The software seamlessly integrates circuit design, electromagnetic (EM) simulation, layout capabilities, and system level modeling, reducing time needed for importing and exporting designs and fixing errors associated with changing tools. Improvements in data analytics allow for rapid analysis and timely design decisions.
PathWave Advanced Design System (ADS) 2020 Update 2.0 Release Notes
Design and Technology Management
Data Display
- Expression Manager is a docking window that displays all equations and trace equations in a table for each data display window. A new filter mode has been added.
Additional improvements:
. Improved equation and trace selection from data display pages
. Added table filter option
. Added variable info panel
- Added new dialog to modify multiple Description axes
IC Interoperability
- Newer Cadence ICADVM 18.10.080 and IC618 have upgraded OA libraries.
Design Editing
- Teardrops now supports angle specification. For more information,
- Added support to create circular keepout object.
- Added AEL functions and examples to create padstacks in library technology.
- Navigator window supports context sensitive menu to include most useful object specific operations.
Circuit Simulation
General
- Envelope simulation improvements:
. Introduction of new modeling pulse-driven technique to better cope with higher memory effects.
- Support of Spectre noise correlation format.
- Modified the custom rule regular expression.
- Changed the rise time and fall time to 0.2 dq UI.
- Use custom rule when specified without having to add it to preset.
- Added the list of BER and "Calculate contour at multiple BER" option.
- Fixed the DDR_PCB table resize issue.
- IBIS model selection now displays the full model name.
- Fixed the issue where two DCD implementations reports shows different results.
- WidthAtBER now gives correct results when the Density is not at center of 2UI in the IBIS-AMI Channel simulation.
ElectroThermal
- ETH now consumes the raw TransientVars::step_reduction_factor, without processing (clamping etc.).
- Fixed the reuse model extraction while using encrypted thermal technology.
HSD Design
SerDes
Introduced the E-O-E (Electrical-Optical-Electrical) integrated work flow with VPIphotonics for Datacom and Telecom markets. The VOL (VPI Optical Link) component must have a valid Simulation: Link_to_VPI license for the co-simulation. This enables the users to consider the optical channel effect in the design of the end-to-end link analysis, such as:
- Nonlinear wavelength-dependent transfer function of Electro-Absorption Modulators (EAM)
- Nonlinearity
- Relative Intensity Noise (RIN)
- Fiber attenuation
- Dispersion
DDR/Memory
- New DDR5 and LPDDR5 solutions with IBIS-AMI modeling for equalizations
- Jitter tracking for optimal DFE clocking with internal phase interpolator training
- Automated DDR5 compliance test on simulated waveforms
- Streamlined memory design workflow such as integrated package setup in to Controller and Memory to reduce wiring
- Controller, Memory, and Termination GUI improvement and group editing for DDR_Termination component for better usability
EM-SI/EM-PI
- Context-Aware Signal Name Matching algorithms in SIPro
- Added delay Description in the results window.
- Added dc frequency (0 Hz) support for Logarithmic frequency plan in Via designer.
- Added option to set number of samples for siodump.
- Component Model Library Tools now work with .brd and odb++ imported PCB data.
- PIPro DC Results Power Tree speed improvements and the ability to handle multiple power rails in one design analysis.
EM Simulation
General
- Added support for Teardrops in EM Simulation flow.
RFPro
- Generate a Sub Circuit schematic from RFPro in Custom Compiler to run a Circuit+EM simulation.
- Analyze the impact of etch bias (over/under etch) without the need for parameterizing the layout.
- Pilot introduction of cross-platform simulations. A Windows/Linux client can submit a simulation to a Linux cluster. In case you have an interest in trying out this new functionality, contact Technical support and guidance will be provided to configure this simulation service.
- Momentum
. The 'Loading Green Functions' step now runs multi-threaded.
. Pilot introduction of a faster Momentum preprocessor. Enable the 'Show Beta Functionality' from the 'Tools > Options > General' tab to have access to the 'Generation 2' as Advanced Simulator Setup option.
- FEM
. The number of threads during the solve is no longer restricted to 8. All physical cores will be used when requested.
. An issue has been fixed in FEM Generation 1 for 'TML' (waveguide) ports. The vertical extent of the waveguide port surface was clipped to the highest/lowest Z in the substrate stack, leading to inaccurate results for microstrip waveguide ports.
. Pilot introduction of FEM Generation 2 simulations with EMPro 3D components placed in ADS layout. Enable the 'Show Beta Functionality' from the 'Tools > Options > General' tab to gain access to this new capability.
Power Electronics
- Model from datasheet
. Added a template to extract a model from a Power MOSFET datasheet.
. Added an example workspace to demonstrate model extraction from a Power MOSFET datasheet. For more information, refer Simulation of Generic Power MOSFET Model Extraction.
- Added a generic power MOSFET component to the Power Electronics library.
- Fixed a bug in the IGBT example workspace.
Power Electronics Professional (PEPro)
- Fixed a bug in the show/hide button in the PEPro Layer Display Settings Panel.
- Fixed a bug in the information icon in the select dataset dialog in circuit excitation.
- Fixed a bug in the closed loop buck converter example workspace.
- Fixed a bug in the field scale properties.
- For more information, see PEPro.
Design Import/Export
- Added support for import of netlists with diode model temperature coefficient parameters.
- Added support for import of LTspice netlists with component values enclosed in curly braces.
PDK Validator
The PDK Validator configuration file is used to specify PDK-specific logic for creating test libraries.
- For PDKs that support placing technology components in a defaults design, use
. pdkv_lib_set_default_design_cell_names()
- For PDKs that require technology components be placed in the schematic, use
. pdkv_lib_set_schematic_test_cell_names() (from this release)
Design Kits
- Added the custom DRC example in Non Linear Demokit (NLD).
- Updated the source of demo_fet1 component in Non Linear Demokit (NLD).
Layout Versus Schematic (LVS)
- Ignore schematic-only components SnP and S2P.
- Ignore Terms and named nets connected to deactivated components.
- Include all shapes on gnd! (including shapes in sub designs) in the connectivity area of the gnd! net.
- Device Recognition: New function to specify the connection from an import technology layer to a work layer in the rule file (dve_connect_import_pin_layer()).
Design Rule Check (DRC)
- Support rule files with connect statements that reference more than 10 work layers.
Calibre DRC
- Support a secure data transfer protocol (sCP).
- Added new functions to specify the rule folder and rule file.
Verification Test Bench (VTB)
- The Single Port VTB (only Source) simulation is now supported. Now, you can create complex modulated sources in SystemVue and use with ADS Circuit Envelope.
- From ADS 2017, to install files that are required for the VTB functionality you need to download a separate VTB installer (for Windows only). For Linux, the VTB installer is bundled with ADS installer.
. It is recommended to download compatible ADS and VTB installers to the same directory. After the download, run the ADS installer. This process will automatically install the VTB functionality.
. If you have already installed ADS and find VTB functionality is missing, then you need to download and install the VTB.
- Upgraded SystemVue 2018 engine in ADS.
. Added the following new VTBs:
.. 5G Advanced Modem Workspaces
.. NB IoT Workspaces
. Updated the name of the existing VTBs:
.. WLAN 11ac Workspaces
- ADS 2019 only supports import of Custom VTB (SystemVue workspace) created using SystemVue 2018 and SystemVue 2018 Update 0.1.
Documentation
Starting with the 2020 release, the online help gets a new user interface. The new UI improves overall online help usability by providing the following key benefits in addition to several other minor benefits:
- Table of Contents Sidebar: Displays collapsible Table of Contents for the entire documentation. The left-double-arrow icon collapses the sidebar, and the right-double-arrow icon displays the sidebar back again.
- PDF Button: Allows you to instantly generate PDFs of the latest documentation anytime, including current page's children pages. Currently, the PDF generation option is available only for 2020 release. For other releases, you can switch to their Printing Manuals page and download the existing PDFs like earlier.
- Product Release Switcher: Allows you to view the current page in other supported releases listed in the drop-down menu. Once you select a release from the drop-down menu, the current page is updated to show the content applicable to the selected release. The Table of Contents is updated as well. With this, you bookmark URL of only one release and then switch to other releases from this drop-down menu.
- Latest Documentation: The documentation available in the new UI is always kept updated for all supported releases. These updates are available to you as soon as they happen at our end. This provides you 24x7 access to the most recent and technically accurate documentation.
The Keysight Technologies, Inc. Advanced Design System (ADS) is the world's leading electronic design automation (EDA) software for RF, microwave, and high speed digital applications. In a powerful and easy-to-use interface, ADS pioneers the most innovative and commercially successful technologies, such as X-parameters* and 3D EM simulators, used by leading companies in the wireless communication and networking and aerospace and defense industries.
For LTE-A, 802.11ac, PCI Express, USB3, radar, and satellite applications, ADS provides full, standards-based design and verification with Wireless Libraries and circuit-system-EM co-simulation in an integrated platform.
Only ADS offers a solution that combines schematic, layout, circuit, electro-thermal co-simulation and three full-wave 3D EM technologies for IC, package, laminate/PCB and 3D EM component co-design in a single-vendor, integrated platform solution that can dramatically improve productivity and significantly reduce costs.
To shorten your design cycles, ADS provides a huge amount of application-specific data. Over 300 examples cover everything from specific application circuits to tutorials on how to get the most out of ADS. DesignGuides integrate the experience and best practices of leading designers to provide you with wizards, pre-configured set-ups and displays, and step-by-step instructions for design applications, and give you easy access to the power of ADS from day one.
PathWave * Advanced Design System (ADS) 2020 is the next major step in delivering new capabilities, new technologies and more improvements to further improve design productivity and efficiency.
* The PathWave software platform facilitates a completely new product development culture that creates an environment where design and test engineers can speak the same language. At Keysight, we call this new product development philosophy TestOps.
TestOps empowers you to develop, deploy, analyze, and release new products more accurately and quickly.
You've just downloaded Keysight ADS, and now you'd like to get up and running in under 10 minutes. In this short video, you will learn how to navigate through the ADS environment to create a new workspace, build a new schematic, and run a simulation. Through an example, you will also learn how to tune your design to optimize the performance.
Keysight Technologies Inc. is the world's leading electronic measurement company, transforming today's measurement experience through innovations in wireless, modular, and software solutions. With its HP and Agilent legacy, Keysight delivers solutions in wireless communications, aerospace and defense and semiconductor markets with world-class platforms, software and consistent measurement science.
Product: Keysight Advanced Design System (ADS)
Version: 2020 Update 2
Supported Architectures: x64
Website Home Page :
www.keysight.comLanguage: english
System Requirements: PC *
Supported Operating Systems: *
Size: 2.1 Gb
System Requirements
Operating System
Practical Minimums: Windows 7 SP1, 64-bit
Recommended Basic: Windows 10, 64-bit
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