Risc Processor With Own Instruction Set Architecture (Isa)

[mitsumi]

Last updated 10/2021
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 714.59 MB | Duration: 1h 39m

Understanding the design of our Instruction Set Architecture and RISC Architecture

What you'll learn
Understand how to design RISC processor
How to create instruction set architecture
Able analyze the complete RISC Architecture
Able to analyze flow of execution of instruction in each module
Requirements
Basic idea on Microprocessors and its terminology
Basic in Digital electronics
Description
In this course, discussing on Instruction set Architecture, how we can built our own ISA, and what are types of instructions, how can specify the address of instruction. How to define Instruction format. And prepared the possible instruction types and naming the opcode as well as giving our own address and naming to the instruction. From this course, we discussed start with features in RISC and what features we need to look, so that get clarity in how to think about processor.Next start with instruction set architecture, think of possible registers, and analyze how we can address specification to all our registers. and think of possible types of instructions by considering addressing modes. that name it as R-type, i-type, J-type, B-type, Load type and Store type. we need to define instruction format to all the types of instructions. in each type there may be combination different instructions like Arthimatic and Logical and shift instructions. here instruction format is discussed with example and position of each register like source register and destination register. Also discussed about Architecture of RISC and individual modules. Analyze the flow of execution of instructions through different modules like Instruction memory unit, Fetch unit, Decoder unit, Register file unit, ALU and Data memory.Instruction Memory unit is nothing but code memory and it contains set of instructions, and these instructions are arranged with opcode, source address, destination address and immediate data with specified analysis.Fetch unit extracts the single instruction at a time and giving to decoder unit. Decoder unit separates fetched instruction in to opcode, source address, destination address and immediate data. And these items are assigned to Register file.Register file contains all the registers and opcodes and mnemanics along with content and memory controller. Content of corresponding source addresses extracted from register file and given to ALU and executes the required operation using opcode given. Result of ALU will store in to Data memory and again back to register file.This course gives complete picture of the RISC processor and its flow.
Overview
Section 1: Introduction
Lecture 1 Preview
Lecture 2 General Features of RISC and ISA
Lecture 3 Features of any computer and our assumptions
Section 2: Design of our own Instruction Set Architecture (ISA)
Lecture 4 Possible Registers
Lecture 5 Types of Instructions ( Addressing modes)
Lecture 6 R-Types of Instructions
Lecture 7 I-Types of Instructions
Lecture 8 J-Types of Instructions
Lecture 9 B-Types of Instructions
Lecture 10 Load -Types & Store - Types of Instructions
Lecture 11 Summarize our own Instruction Format
Section 3: Architecture of RISC
Lecture 12 Architecture of the RISC
Lecture 13 Instruction Memory Unit
Lecture 14 Fetch Unit
Lecture 15 Decoder Unit
Lecture 16 Register File
Lecture 17 ALU
Lecture 18 Data Memory
Lecture 19 Control Unit
Every Undergraduate & Graduate Electronics & Computer science students,Students who want to design their own RISC processor

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