Keysight Advanced Design System (ADS) 2020 Update 1.1

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Keysight Advanced Design System (ADS) 2020 Update 1.1



Keysight Advanced Design System (ADS) 2020 Update 1.1 | 2.6 Gb

Keysight Technologies Inc. has announces the availability of Advanced Design System (ADS) 2020 Update 1.1. This release introducing the world's leading DDR5/LPDDR5 simulation solution. The Memory Designer workflow has been expanded to cover the latest memory standards, and the DDR Bus simulator has been enhanced to handle IBIS-AMI models in bit-by-bit mode.



Feature Updates
General
- Improved workspace performance when including many libraries on a network path.
- Added support for third-party version control systems to support tagging.
- Support "Patch" components.
Data Display
- Data Display Expression Manager and Expression Hierarchy improvements. Added new feature to change dataset reference in equations.
- Added Equation Import from text file. For more information, see Importing Equations.
- Improved Copy Cell and Reference operations to support references in Data Display files.
Design Editing
- Added Tear drops functionality, a special connection pattern that optimize the trace-to-pad, trace-to-via connection and improve the manufacturability of the layout.
- For more information, see Teardrops.
- Added Tear drop AEL Functions to add, modify, and remove tear drop to selection. For more information, see Teardrop Functions.
- Added AEL functions for the following:
. To get end or corner for line segment of an interconnect. For more information, see Interconnect Creation Functions.
. To rotate all the selected objects in the given context added the db_rotate_selected_objects() function.
. To use in macro recording when user places an unconstrained via
. To draw a Trace (with AEL commands) using a Line Type.
. To extract Keepout information. For more information, see Keepout Functions.
. To get ground plane outline points.
. To access via name, template name, start stop layer of a PCB Via instance.
. AEL iteration inside interconnect, get layer, via information, and net.
- Constraint Manager Enhancements:
. Support for line type based clearance rule.
. Support of priority and validity to the clearance and via rules.
Circuit Simulation
Models
- Support of TMI models
- XL now affects computations of stress effects in BSIMSOI models
Circuit Envelope
- Introduction of Compact Test Signals to accelerate Envelope simulations when using a modulated source.
- Convolution in Envelope provides a more accurate way of modeling file-based S-parameters.
ElectroThermal
- FloorPlanner results are now accurate when power specified is in [mW/uW/pW].
HSD Design
DDR/Memory
- DDR5 memory design support
- IBIS-AMI model support for equalization
- Bit-By-Bit simulation mode for DDR Bus Simulator
- Write Leveling (delay file) support
- Data Bus Inversion (DBI) support
- Automated signal property assignment for third party PCB data
- Improved group editing for every Memory Designer component
EM-SI/EM-PI
- PIPro AC and SIPro Analysis continued improvements to reduce parasitics at the external ports, and component ports provide increased accuracy for PDN impedance.
- Via back-drill information can be imported from Allegro PCB version 17.2 and higher using ADFI export.
- PIPro AC and SIPro Analysis support non-updatable (embedded) components for all component model types.
- SIPro accuracy improvement for differential lines with vias having a common clearance hole.
EM Simulation
RFPro
- Speed improvements when opening RFPro or switching component roles.
- FEM
. The FEM solver is now available in RFIC platforms to complement Momentum for FBAR filters or Wafer-Level Packaging.
. Pilot introduction of a new FEM solver: Generation 2
.. Dramatically decreases the pre-processing time.
.. New Mesh Domain Optimization mode for FEM to automatically decrease the simulation space when selecting nets or components while keeping an accurate ground return path.
.. Supports encrypted LTD substrates.
- Momentum
. The new, default, 'Automatic' thick conductor and via conductor model option speeds up the simulation of designs with large ground/power plane(s) and many ground/power vias.
- Far-Field Results
. View Directivity and Gain patterns in 3D.
. Create 2D Descriptions from 3D far-field patterns.
. Export Far Field data to file.
- Python Scripting
. The 2020 releases are the last releases with Python 2.7 as Python 2.7 is reaching its end-of-life. The 2021 releases will use Python 3.7. A pilot release with Python 3.7 is available for download. Contact Technical Support for further guidance.
Power Electronics
Power Electronics Professional (PEPro)
- New test bench to Description Radiated EMI versus frequency and angle for pre-compliance testing of PCB layout candidates
- Improved the Conducted EMI results data display for better spectral accuracy and noise level.
- Fixed the PEPro bugs. For example, display text in the Undo button.
Design Translation
- Fixed the issue where the netlist file import failed on Windows operating systems when there was a space in the input file's path.
- Fixed the issue where the file name along with the file path was being used instead of just the file name in the NetlistInclude component's IncludeFile field, generated during netlist file import.
- Fixed the LTspice import bugs. For example, the simulator reserved words are fixed.
Design Rule Check (DRC)
Assura DRC
- Added support for GDS datatype while loading Assura DRC output files.


Issues Addressed
ADS 2020 Update 1.1 addresses issues related to Circuit Simulation, Data Display, Design andTechnology Management, Design Editing, ElectroThermal, and EM Simulation.
Circuit Simulation
- Gcc compiler and shared library version mismatch issue can be fixed using the below workaround.Workaround: Set the environment as: setenv LD_LIBRARY_PATH $HPEESOF_DIR/tiburonda/tools/linux_x86_64/lib64:$ LD_LIBRARY_PATH
- Fixed the disruptive flow for DDR PCB Component where the component (whether pointing to an SIProgenerated cell or S-data file) or the channel ID comes back as blank.
Data Display
- Improved update dataset references.
- Fixed Expression Manager refresh using multiple data-display windows.
- Improved updating expressions for Change Datasets.
Design Editing
- Fixed the Smart Mount Pcell crash where master design is null.
- Fixed the issue to now create planes partially in and partially out of a keepout, or completely out of akeepout.
- Plane 2 Plane clearance from Constraint Manager now works as expected.
Design and Tech Management
- Fixed possible library rename crash when using workspace load performance improvements.
- Fixed the "DDS File Load error" issue when using adding references to current selection.
- Fixed Archive Cell possibly selecting all libraries to archive.
ElectroThermal
- Checks the number of "independent" power sources in ETH against licensing limits.
- ETH now consumes the raw TransientVars::step_reduction_factor, without processing (clamping etc.).
- Transient and Circuit Envelope ElectroThermal simulations now aborts or exits within less than aminute.
EM Simulation
- FEM: Updated the routine that computes the mutual inductance between line segments with routinesthat are more stable when the segments are parallel.
- RFPro: FEM Generation 2 now correctly deals with a material where the 'resistance' specification isused.
- PIPro: Fixed an E-Field Description failure for multi-pin components.
- SIPro: Fixed the backdrill via definition issue.
- SIPro: Fixed an issue that prevented starting a simulation.

Advanced Design System (ADS) is the world's leading electronic design automation software for RF, microwave, and high-speed digital applications. ADS pioneers the most innovative and powerful integrated circuit-3DEM-thermal simulation technologies used by leading companies in the wireless, high-speed networking, defense-aerospace, automotive and alternative energy industries. For 5G, IoT, multi-gigabit data link, radar, satellite and high-speed switched mode power supply designs, ADS provides an integrated simulation and verification environment to design high-performance hardware compliant with the latest wireless, high speed digital and military standards.
This video shows you how to use basic signal integrity (SI) analysis techniques such as eye diagrams, S-parameters, time-domain reflectometry (TDR) and single pulse response to solve signal integrity problems.


Keysight Technologies Inc. is the world's leading electronic measurement company, transforming today's measurement experience through innovations in wireless, modular, and software solutions. With its HP and Agilent legacy, Keysight delivers solutions in wireless communications, aerospace and defense and semiconductor markets with world-class platforms, software and consistent measurement science. The company's nearly 10,500 employees serve customers in more than 100 countries.
Product: Keysight Advanced Design System (ADS)
Version: 2020 Update 1.1
Supported Architectures: x64
Website Home Page :
www.keysight.com

Language: english
System Requirements: PC *
Supported Operating Systems: *
Size: 2.6 Gb


The following are Keysight recommended configurations:
Recommended
RAM: 32 GB RAM or higher
Hard Disk Space: 512 GB free disk space or greater
Processor: 64-bit, multi-core CPU
Screen Resolution: 1080p (1920x1080) or 4k (3840x2160) display resolution with true color
Model Development dependency for model development: Visual Studio 2017
Minimum
RAM: 8 GB RAM or higher
Hard Disk Space: 20 GB free disk space or greater
Processor: 64-bit CPU
Screen Resolution: 1024x768 display resolution with true color
Model Development dependency for model development: Visual Studio 2017
Operating System
- Windows 7 Enterprise (64-bit)
- Windows 10 Enterprise (64-bit)

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