Cadence SPB Allegro and OrCAD 17.20.000-2016 HF056 (x64)
Cadence SPB Allegro and OrCAD 17.20.000-2016 HF056 (x64) | 3.8 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled a new of improvements to the Cadence SPB Allegro and OrCAD 17.20 families of products aimed at boosting performance and productivity through improvements features and big fixed issues.
2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix
2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not to flow from pstchip
2092872 ADW PART_MANAGER Import DE-HDL Sheets stops responding
2088975 ALLEGRO_EDITOR 3D_CANVAS Bending in 3D Canvas causes PCB Editor to crash
2088577 ALLEGRO_EDITOR COLOR Export color nets does not write all the nets in param file
2028867 ALLEGRO_EDITOR DFM False DFF Trace to Thru via pad spacing DRC
2037361 ALLEGRO_EDITOR DFM Soldermask features drawn with a line do not DRC to pin, via, or shape soldermask features
2077913 ALLEGRO_EDITOR DRC_CONSTR When running a simple SKILL command, the tool will run for a very long time
2079642 ALLEGRO_EDITOR DXF Drill symbols are rotated in exported DXF in release 17.2-2016
2083493 ALLEGRO_EDITOR MANUFACT Manufacture - Cross section chart is not readable for rigid-flex designs
2073607 ALLEGRO_EDITOR MCAD_COLLAB IDX_IN batch program to allow a batch update of an .idx file
2095632 ALLEGRO_EDITOR MULTI_USER Design server on Symphony stops responding and cannot be closed or downloaded
2098221 ALLEGRO_EDITOR MULTI_USER Symphony Server Manager allows connection to databases deleted from the project area
2087315 ALLEGRO_EDITOR NC Backdrill exclusions raised on pins of a component
1947929 ALLEGRO_EDITOR OTHER The 'show measure' function crashes when measuring pin to pin distance
2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses
2089470 ALLEGRO_EDITOR REPORTS Summary report shows the exclamation character (!) in the middle of numbers and words
2067324 ALLEGRO_EDITOR SHAPE Netin crash during third-party Netlist import
2075191 ALLEGRO_EDITOR SHAPE Delete islands in the design: update out of date shapes and Database Check
2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192
2043825 ALLEGRO_EDITOR UI_GENERAL Custom toolbar settings are not retained upon restart of Allegro PCB Designer
2090185 ALLEGRO_EDITOR UI_GENERAL UI setting in INI file not retained
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design Padstack is limited to 20 characters
2099070 ALLEGRO_EDITOR UI_GENERAL UI setting not working properly, Icons missing after restart.
2088484 APD DATABASE Some objects (Vias and Cline) cannot be modified (edit, delete and slide) in the mcm database
1951623 APD DEGASSING Shape Degassing fails with specific Void to Shape boundary value
2081363 APD DEGASSING Cannot degas for specific shape
2083498 APD WIREBOND Cannot wire bond from a diepad to another diepad on the same component
2086589 CAPTURE NETLIST_ALLEG The generate the CM enabled files from the command line using pstswp.exe.
2098248 CAPTURE NEW_SYM_EDITO Ignore pin is not working for individual pins in Edit pin spreadsheet when edited for all pins
1773047 CIS PART_MANAGER Pin numbers and names for DNI parts will get disappeared in variant view mode if they are relocated in part editor
2003818 CIS PART_MANAGER Pin name and number of 'do not stuff' parts are not visible in the View variant mode
2076265 CIS PART_MANAGER Variant view pinnr/pinname disappears
2076282 CIS PART_MANAGER View variant does not show pinnr and pinname
2083394 CIS PART_MANAGER No pin names and numbers on variant view for specific parts
2090027 CONCEPT_HDL CORE Cut and move of split hierarchical symbol to another page results in error due to lock or write permission issues
2071355 ORBITIO ALLEGRO_SIP_I Dummy nets creation in die after performing Merge Updated SiP
2067703 PCB_LIBRARIAN OTHER PDV crashes immediately for vector pins if MSB is lower than LSB
2041348 PCB_LIBRARIAN SYMBOL_EDITOR Grid setting change cannot be saved in new Symbol Editor
2041365 PCB_LIBRARIAN SYMBOL_EDITOR Improve copy drawing objects in new Symbol Editor
2067931 PCB_LIBRARIAN SYMBOL_EDITOR New symbol editor grid issue: documentation grid spacing value changes
2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbol font text and appearance different when placed in Schematics
1919298 PSPICE FRONTENDPLUGI Capture crashes on archiving project
1953001 PSPICE FRONTENDPLUGI Archive project causes Capture crash.
2035572 PSPICE FRONTENDPLUGI Crash on archiving project
2041286 PSPICE FRONTENDPLUGI Archive project crashes when using lib as global.
2081796 PSPICE FRONTENDPLUGI 'Archive Project' crashes Capture in release 17.2-2016, HotFix 053
2106017 PSPICE FRONTENDPLUGI Capture crashes when archiving PSpice-enabled project
2051450 PSPICE PWL PWL Sources application: pop-ups and messages when browsing and placing source
2090021 PSPICE PWL Modeling Application - Sources - PWL Sources Dialog is not properly displayed
2094548 PSPICE SIMULATOR Model undefined error on TL494
2058018 SCM PACKAGER Reference designator mismatch in 'exportsch' schematics and board file
1955868 SIP_LAYOUT STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS
2081914 SIP_LAYOUT STREAM_IF Release 17.2-2016: GDSII stream out drops shapes
2013647 SYSTEM_CAPTURE CANVAS_EDIT Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections
About SPB Allegro and OrCAD 17.20-2016. Cadence Design Systems announced new capabilities for OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
This OrCAD portfolio includes new advanced technology enabled for integrated rigid-flex planning, design and real-time visualization, as well as built-in translators that enable direct design imports from select EDA vendors. PSpice Designer now supports system-level simulation using C/C++/SystemC and VerilogA, via the new PSpice compact model interface. This enables hardware/software virtual prototyping so that electrical engineers can design and simulate intelligent IoT devices. OrCAD is the only fully scalable PCB design solution available in the market that seamlessly transitions from mainstream to enterprise PCB solution with the Allegro environment.
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD portfolio uses a new multi-stack-up database capability and extensive in-design inter-layer checks, which helps users avoid errors introduced through manual checking. The OrCAD portfolio also features enhancements targeted towards improving PCB editors' productivity and ease-of-use in padstack editing, constraint management, shape editing and in-design DRCs. To address efficiency needs, the portfolio includes an advanced design differencing engine that enables design review with global teams using state of art visuals. Finally, to give designers more control over their design component annotation process, advanced annotation and auto-referencing capabilities are now available.
Allegro 17.2 release introduces many new capabilities for Flex and Rigid-Flex designs.
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence SPB Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF056
Supported Architectures: x64
Website Home Page :
http://www.cadence.comLanguage: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence SPB Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 3.8 Gb
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