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SECÇÃO INFORMATICA => Software => Utilitários => Tópico iniciado por: mitsumi em 04 de Setembro de 2019, 14:46

Título: Cadence Design Systems Sigrity 2018.04 (x64)
Enviado por: mitsumi em 04 de Setembro de 2019, 14:46

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Cadence Design Systems Sigrity 2018.04 (x64) | 6.8 Gb

Cadence Design Systems,  has launched the hotfix 4 for Cadence Sigrity 2018 release. The 2018 release includes new 3D capabilities that enable PCB design teams to accelerate design cycles while optimizing cost and performance.

        - 3D_EM 3D-EM fails to run Broadband SPICE with embedded Touchstone models
- 3D_EM In SoC deembedding flow, generating spds does not include max frequency in .spds
- 3D_EM 3D-EM full wave extraction stops with Error 80
- OPTIMIZEPI MCP Editor does not display pin/net information
- POWERDC VOL in PWT_DCDC_PINS property
- POWERDC IR drop result display is wrong in PowerDC
- POWERDC PowerDC does not produce same current in a segment as that in vias on both sides of the segment
- POWERSI Performing extraction in PowerSI results in two polygons are too close error
- POWERSI PowerSI simulation fails with input polygon error and two polygons are too close error
- POWERSI XtractIM simulation generates an error stating two polygons are too close to one another
- POWERSI PowerSI Network Parameter Viewer Smith Chart View stops responding in Linux when changing back to Amp
- POWERSI PowerSI resonance mode results are not changing with frequency
- POWERSI PowerSI stops responding while saving design file
- POWERSI Spikes are found in DCFitted curves
- POWERSI DC point failure occurs in PowerSI
- POWERSI TCL command separateMultiplyConnectedPolygons does not work for customer case
- POWERSI Activating PDC option causes PowerSI to stop responding
- POWERSI Add support for square brackets in TCL commands
- POWERSI PowerSI stops responding on the sample file in SIGRITY2018HF3
- POWERSI PowerSI simulation stops with 'The factorization failed' error
- SPEED2000 Pad capacitance extraction results in two capacitor values being randomly generated as DIMM PAD model in SPEED2000
- SPEED2000 SRC report cannot be generated in SIGRITY2017 and SIGRITY2018 releases
- SPEED2000 SPDSIM SPICE solver stops responding on a special case
- SYSTEMSI SystemSI - PBA does not calculate jitter and noise margins correctly for READ cycle
- SYSTEMSI SPEED2000 Block behavior is incorrect in the latest release of SystemSI
- TRANSLATOR Translator interprets 'Regions' incorrectly while importing the PCBDoc file
- TRANSLATOR Add model name assignment from ODB++
- XCITEPI Fix the wrong nodes issue in TSV level 4 model
- XTRACTIM Diffpair FEXT calculation does not work properly in XtractIM EPA mode
- XTRACTIM Fly_bonding wire pads appear twice in XtractIM SPICE model
- XTRACTIM 'Per Pin L Extraction Error' occurs when running XtractIM
- XTRACTIM Reading SiP (Lead-Frame) design inside XtractIM
- XTRACTIM XtractIM does not generate correct X call for capacitor when all nets associated with capacitor are not enabled   
   

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Cadence Sigrity 2018 release       includes new 3D capabilities that enable PCB design teams to accelerate design cycles while optimizing cost and performance. A unique, 3D design and 3D analysis environment integrating Sigrity tools with Cadence Allegro technology provides a more efficient and less error-prone solution than current alternatives utilizing third-party modeling tools, saving days of design cycle time and reducing risk. In addition, a new 3D Workbench methodology bridges the gap between the mechanical and electrical domains, allowing product development teams to analyze signals that cross multiple boards quickly and accurately.

Since many high-speed signals cross PCB boundaries, effective signal integrity analysis must encompass the signal source and destination die, as well as the intervening interconnect and return path including connectors, cables, sockets and other mechanical structures. Traditional analysis techniques utilize a separate model for each piece of interconnect and cascade these models together in a circuit simulation tool, which can be an error-prone process due to the 3D nature of the transition from the PCB to the connector. In addition, since the 3D transition can make or break signal integrity, at very high speeds designers also want to optimize the transition from the connector to the PCB or the socket to the PCB.

The Sigrity 2018 release enables designers to take a holistic view of their system, extending design and analysis beyond the package and board to also include connectors and cables, all of which can impact optimization of the high-speed interconnect. An integrated 3D design and 3D analysis environment allows PCB design teams to optimize the high-speed interconnect of PCBs and IC packages in the Sigrity tool and automatically implement the optimized PCB and IC package interconnect in Allegro PCB, Allegro Package Designer, or Allegro SiP Layout without the need to redraw. Until now, this has been an error-prone, manual effort requiring careful validation. By automating this process, the Sigrity 2018 release reduces risk, saves designers hours of re-drawing and re-editing and can save days of design cycle time by eliminating editing errors not found until the prototype reaches the lab. This reduces prototype iterations and potentially saves hundreds of thousands of dollars by avoiding re-spins and schedule delays.

A new 3D Workbench utility available with the Sigrity 2018 release bridges the mechanical components and the electronic design of PCB and IC packages, allowing connectors, cables, sockets and the PCB breakout to                                                                                                                                                                                                          be modeled as one with no double counting of any of the routing on the board. Interconnect models are divided at a point where the signals are more 2D in nature and predictable. By allowing 3D extraction to be performed only when needed and fast, accurate 2D hybrid-solver extraction to be performed on the remaining structures before all the interconnect models are stitched back together, full end-to-end channel analysis can be performed efficiently and accurately of signals crossing multiple boards.

In addition, the Sigrity 2018 release offers Rigid-Flex support for field solvers such as the Sigrity PowerSI® technology, enabling robust analysis of high-speed signals that pass from rigid PCB materials to flexible materials. Design teams developing Rigid-Flex designs can now use the same techniques previously used only on rigid PCB designs, creating continuity in analysis practices while PCB manufacturing and material processes continue to evolve.

Sigrity technologists guide you step by step on how to design and verify your automotive Ethernet serial links using the Sigrity serial link analysis methodology. Simulating and verifying your designs meet compliance standards before you go to the lab will reduce design re-spins saving significant time and money. Ensure your automotive module will hit the market ahead of your competitors. 

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products-from chips to boards to systems-in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

Product: Cadence Design Systems Sigrity
Version:   2018.04
Supported Architectures: x64
Website Home Page :

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Language: english
System Requirements: PC *
Supported Operating Systems: *
Size: 6.8 Gb

        Windows Requirements

Operating System
Microsoft Windows 7 all versions (64-bit); Windows 8 (64-bit) (All service packs); Windows 10 (64-bit); Windows 2008 Server R2; Windows 2012 Server (All service packs).
Recommended Software
Microsoft Internet Explorer 9.0 or later
Minimum Hardware
Intel  IA-64 Compatible (includes P4 EMT and AMD Opteron)
8 GB RAM
Virtual memory at least twice physical memory
50 GB free disk space
1,024 x 768 display resolution with true color (16bit color)
Broadband Internet connection for some serviceEthernet card (for network communications and security hostID)
Three-button Microsoft-compatible mouse
Recommended Hardware
Intel 4th Generation Core (Haswell) or AMD Kaveri
64 GB RAM or higher; 192 GB of RAM or higher is recommended for 3D-EM
500 GB free disk space
SSD is recommended for primary operating system (OS) and simulation working directory
Dedicated graphics card with 1 GB video memory or higher
Large monitor (or two) with Full HD resolution or higher
Broadband Internet connection for some services
Three button mouse with scroll wheel
Full size keyboard   

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